# Low Noise Amplifiers

Contents

LNA is the first gain block in the receive(Rx) chain of a transceiver. It has a significant impact on the noise performance of the Rx chain.

## Why low noise amplifier?

In RF circuits noise is characterized by noise figure or noise factor.

Noise factor at the input of the Rx chain is given by

(1)

where,

Noise factor of LNA

Cascaded noise factor of subsequent block of Rx except LNA

Power gain of LNA

Eq.(1) suggests higher gain of LNA is required to supress the input referred noise coming for subsequent stages after LNA in Rx chain. This improves NF and hence sensitivity of Rx front-end. Therefore high gain and low noise figure are very important LNA design specifications for best noise performance of any receiver.

## LNA Design Specifications

- Noise figure – directly impacts the sensitivity of a receiver
- Gain – reduce the impact of noise of subsequent circuits after LNA, and thus the sensitivity of the receiver
- Linearity(IIP3/IIP2 and P1dB) – decides the blocking performance
- Input/Output impedance matching – minimize the reflections
- Bandwidth
- Stability
- Power consumption – should be a low as possible to improve battery life.

## LNA Topologies

- Resistive termination
- Common gate configuration
- Series-Shunt feedback
- LNA with source degeneration

In the following analysis, only thermal noise of MOS transistor and resistors are considered. In the real design, gate induced noise, and other noise sources need to be considered for accurate results. Flicker noise, most of times is shaped out by passive networks for narrow band circuits at radio frequencies and can be ignored.

### LNA with resistive termination

Well suited topology for broadband LNA design. It provides input impedance matching Schematic of the LNA with resistive termination is shown in Figure 1a. The equivalent circuit of resistive termination LNA is shown in Figure 1c.

Gain of LNA,

(2)

Noise Factor of LNA is given by

(3)

where,

noise power at the input of LNA due to the source

noise power added by the LNA referred to the output

(4)

From Eq.(3),

(5)

where, . When , then noise factor is

(6)

Therefore the noise figure of Resistive terminated LNA is > 3dB.

### Common gate configuration

A common gate configuration LNA is shown in Figure 2a. The equivalent circuit is shown if Figure 2c.

The gain of LNA is,

(7)

(8)

Noise factor

MOSFET channel noise only considered here for NF calculation.

Noise power added by the circuit referred to the output is ,

Noise power at input

Noise factor of the circuit is

(9)

When , noise factor is

(10)

[1] [2] [3]

## Bibliography

[Bibtex]

```
@ARTICLE{Shaeffer:JSSC1997:568846,
author={Shaeffer, D.K. and Lee, T.H.},
journal={Solid-State Circuits, IEEE Journal of},
title={A 1.5-V, 1.5-GHz CMOS low noise amplifier},
year={1997},
volume={32},
number={5},
pages={745-759},
keywords={CMOS analogue integrated circuits;Global Positioning System;UHF amplifiers;UHF integrated circuits;integrated circuit noise;radio receivers;0.6 micron;1.5 GHz;1.5 V;22 dB;3.5 dB;30 mW;CMOS low noise amplifier;GPS receiver;LNA architecture;UHF;global positioning system receiver;induced gate noise;CMOS technology;Frequency;Global Positioning System;Low-noise amplifiers;Microwave amplifiers;Noise figure;Power dissipation;Semiconductor device noise;Semiconductor optical amplifiers;Working environment noise},
doi={10.1109/4.568846},
ISSN={0018-9200},}
```

[Bibtex]

```
@ARTICLE{Nguyen:TMTT2004:1295142,
author={Trung-Kien Nguyen and Chung-Hwan Kim and Gook-Ju Ihm and Moon-Su Yang and Sang-Gug Lee},
journal={Microwave Theory and Techniques, IEEE Transactions on}, title={CMOS low-noise amplifier design optimization techniques},
year={2004},
volume={52},
number={5},
pages={1433-1442},
keywords={CMOS integrated circuits;UHF amplifiers;UHF integrated circuits;circuit optimisation;integrated circuit design;integrated circuit noise;network topology;0.25 micron;0.7 mA;1.25 V;1.35 dB;1.6 mA;12 dB;900 MHz;CMOS low noise amplifier design;CMOS technology;NMOS transistor;cascode topology;noise matching;noise parameter;optimization technique;power constrained noise optimization;power gain;simultaneous noise input matching;third order intermodulation product;CMOS technology;Design optimization;Equations;Gain measurement;Impedance matching;Low-noise amplifiers;Noise measurement;Power measurement;Topology;ZigBee},
doi={10.1109/TMTT.2004.827014},
ISSN={0018-9480},}
```

[Bibtex]

```
@ARTICLE{5443550,
author={Qiang-Tao Lai and Jun-Fa Mao},
journal={Microwave and Wireless Components Letters, IEEE}, title={A 0.5 #x2013;11 GHz CMOS Low Noise Amplifier Using Dual-Channel Shunt Technique},
year={2010},
volume={20},
number={5},
pages={280-282},
keywords={CMOS analogue integrated circuits;MMIC amplifiers;UHF amplifiers;impedance matching;low noise amplifiers;CMOS low noise amplifier;LNA;dual-channel shunt technique;frequency 0.5 GHz to 11 GHz;gain 10.2 dB;noise figure 3.9 dB to 4.5 dB;power 14.4 mW;size 0.18 mum;wideband input impedance matching;CMOS;dual-channel shunt;low noise amplifier (LNA);ultra-wideband (UWB)},
doi={10.1109/LMWC.2010.2045592},
ISSN={1531-1309},}
```